1. Field of the Invention
The present invention relates to a decoder circuit of semiconductor memory device, more particularly, it relates to a decoder circuit having a simplified circuit arrangement enabling an all selection mode of word lines or bit lines.
2. Description of the Related Art
As is well-known, a decoder circuit is used for selecting the word line or bit line in a semiconductor memory device. In the normal selection mode, a row decoder circuit selects the word line and a column decoder selects the bit line. The all selection mode of word lines or bit lines is used for testing the semiconductor memory device. Accordingly, it is necessary to provide means for generating this mode in the decoder circuit.
Problems have arisen, however, regarding the generating means for the all selection mode in the decoder circuit. That is, this generating means becomes a hindrance to the compacting of space and the reduction of power consumption.